1. Technical Field
The present invention relates to a test apparatus and a test method. In particular, the present invention relates to a test apparatus and a test method for adjusting timing of test signals supplied to a device under test.
2. Related Art
A test apparatus inputs an operation clock signal to a device under test to cause the device under test to operate according to the operation clock signal. Specifically, the operation clock signals are synchronized between the test apparatus and the device under test, and so the test apparatus can supply the test signal to the device under test based on the operation clock signal or acquire an output signal from the device under test based on the operation clock signal.    Patent Document 1: Japanese Patent Application Publication No. H06-188635
Depending on the type of device under test, operation clock signals can be generated by independent oscillation circuits to operate independently from the test apparatus. In this case, the operation clock signals cannot be synchronized between the test apparatus and the device under test. Therefore, the test apparatus cannot supply the device under test with a test signal and cannot acquire the output signal from the device under test.
Patent Document 1 proposes adjusting the waveform of a signal by controlling a frequency divider according to values stored in a memory. This technique simply requires storing one cycle of data in the memory, and can therefore decrease the amount of memory necessary for waveform shaping. However, Patent Document 1 merely describes a waveform shaping method, and does not describe how signals can be synchronized by applying this waveform shaping.
Furthermore, if the device under test has a plurality of clock domains, the phase of the test signal for each clock domain cannot be synchronized.